A grid array interface (GAI) is used as a means for interfacing or connecting high-density integrated circuits (ICs) and/or other high pin-out electronic components or modules to a carrier circuit or to a circuit interconnect in many modern high-density electronic packaging applications. Additionally, GAIs are employed to connect a circuit interconnect to a carrier circuit and occasionally to connect components to components. Examples of such GAIs include, but are not limited to, a ball grid array (BGA) and a pin grid array (PGA). An example of a carrier circuit includes a printed circuit board (PCB) while an example of a circuit interconnect includes a flexible, multi-conductor, interconnect, known as a ‘flex’ circuit. The GAI provides a high-density, parallel electrical interface between essentially any pair of the electrical component, the carrier circuit, and the circuit interconnect. A circuit interconnect, such as a flex circuit equipped with a GAI, is referred to as a grid array interconnect.
For example, a typical grid array interconnect may comprise a BGA located at one end of a flex circuit. The BGA comprises a first 2-dimensional array of electrical contacts or pads, a second 2-dimensional pad array similar to the first pad array, and an array of conductive bumps or spheroids, typically solder balls, bridging or connecting between the two pad arrays. In particular, the first pad array may be arranged on a connection surface of a circuit element such as, but not limited to, an IC package, an electronic module, or a PCB. The second or ‘mating’ pad array may be located on a connection surface of the flex circuit to which the circuit element is to be connected. The solder ball array mechanically and electrically connects the first and second pad arrays to one another forming the BGA of the grid array interconnect. A grid array interconnect employing the PGA is similar in concept to the BGA equipped interconnect except that an array of pins replaces the pad array on one of the connection surfaces while the second pad array on the other connection surface is replaced by an array of holes or sockets to receive the pins. The pins also replace the array of bumps or spheroids (i.e., solder balls).
Grid array interconnects are characterized by having an array depth (i.e., a number of rows in the grid array) and a ‘pitch’ or spacing between columns in the array. Unfortunately in such grid array interconnects, a practical limit to the array depth is often encountered in many cases. To overcome practical array depth limitations, typically either the pitch of the array is increased, additional conductor layers and vias are added to the circuit interconnect, or the circuit interconnect is made wider than the GAI to allow access to rows from sides of the array in addition to an end of the grid array. Increasing pitch tends to decrease an overall density of the array. Adding one or more conductor layers to produce a multilayer circuit allows lower layers to bypass the first rows and access subsequent rows. However, adding layers may greatly increase the cost of the grid array interconnect and may prove impractical or ill advised for certain high frequency applications. Similarly, increasing a width of the circuit interconnect to allow access to the array from multiple sides may not be permissible in some cases, especially where a space for the grid array interconnect is at a premium.